Designing Clustered Multiprocessor Systems under Packaging andTechnological

Packaging technologies impose various physical constraints on bisection bandwidth and channel width of a system whereas processor and interconnect technologies lead to certain throughput and latency demands on the system performance. Earlier studies in literature have either fo-cused on only at interconnections or proposed hierarchical/clustered interconnections with limited packaging constraints. Pinout technologies and capacity of packaging modules have been ignored, often leading to conngurations which are not design-feasible. In this paper, we propose a new supply-demand framework for multiprocessor system design by considering packaging, processor, and interconnect technologies in an integrated manner. The elegance of this framework lies in its parameterized representation of diierent technologies. For a given set of technological parameters the framework derives the best connguration while considering practical design aspects like maximum board area, maximum available pinout, xed channel width, and scalability. In order to build a scalable parallel system with a given number of processors, the framework explores the design space of at k-ary n-cube topologies and their clustered variations (k-ary n-cube cluster-c) to derive design-feasible conngurations with best system performance. The study identiies processor board area, supported channel width, board pinout density, and router pinout as critical parameters and analyzes their impact on deriving design-feasible and best conngurations. For a wide range of parameters, it is shown that best conngurations are achieved with cluster-based systems with 2-8 processors per cluster and 3D-5D inter-cluster interconnection.